********************************************************************* ADVANCE PROGRAM & CALL FOR PARTICIPATION ********************************************************************* Workshop on Network Processors & Applications - NP3 http://www.cse.wustl.edu/NP3/ February 14-15, 2004 Madrid, Spain Held in conjunction with HPCA 10 - The 10th International Symposium on High-Performance Computer Architecture http://www.ac.uma.es/hpca10/ February 14-18, 2004 NEWS * Advance registration deadline is: 23:59pm GMT (~7pm EST), Friday, January 16, 2004 HIGHLIGHTS The workshop will feature: * 13 original research papers, and 4 industry presentations * A keynote address by Nick McKeown of Stanford University * An invited talk * A moderated industry panel session OVERVIEW Network processor design is an emerging field with challenges and opportunities both numerous and formidable. The goal of this workshop is to provide a forum for scientists and engineers from academia and industry to discuss their latest research in the architecture, design, programming, and use of these devices. ADVANCE PROGRAM SATURDAY, FEBRUARY 14 ********************* 1:25-1:30 : Opening remarks 1:30-3:00 : Session 1, Hardware 1 Supporting Mixed Real-Time Workloads in Multithreaded Processors with Segmented Instruction Caches Patrick Crowley Washington U Efficient Packet Classification with Digest Caches Francis Chang, Wu-chang Feng, Wu-chi Feng and Kang Li OGI, U Georgia Towards a Flexible Network Processor Interface for RapidIO, Hypertransport, and PCI-Express Christian Sauer, Matthias Gries, Jose Ignacio Gomez and Kurt Keutzer Infineon, UC-Berkeley, UCM 3:00-3:30 : Break 3:30-4:30 : Invited Talk 4:30-4:45 : Short Break 4:45-6:00 : Session 2, Industry Presentations GEP2C02: A Network Processor for Real-time Content Switching You-Sung Chang, Hun-Seung Oh, Ju-Hwan Yi, Jun-Hee Lee, Seung-Wang Lee, Jung-Bum Chun, Chong-Min Kyung Paion Co. Essential Network Search Engine Features for High Speed NPU-based Packet Searching Michael Miller, Dave Cech and Scott Darnell IDT Taming the Network Processor: Challenges for Developing Reusable Network Software Larry Huston Intel Using Network Processors to Improve Scalability and Availability of Routing/Signaling Protocols Hormuzd Khosravi, Raj Yavatkar, Sanjay Bakshi, Manasi Deval, Rajeev Muralidhar, Suhail Ahmed Intel SUNDAY, FEBRUARY 15 ******************* 8:25-8:30 : Remarks 8:30-9:30 : Session 3, Performance & Modelling 1 Pipeline Task Scheduling on Network Processors Mark A. Franklin and Seema Datar Washington U A Framework for Design Space Exploration of Resource Efficient Network Processing on Multiprocessor SoCs Matthias Grunewald, Jorg-Christian Niemann, Mario Porrmann and Ulrich Ruckert U Paderborn 9:30-10:00 : Break 10:00-11:00 : Keynote Address Network Processors and their Memory Nick McKeown Stanford U 11:00-11:15 : Short Break 11:15-12:00 : Session 4, Performance & Modelling 2 Application Analysis and Resource Mapping for Heterogeneous Network Processor Architectures Ramaswamy Ramaswamy, Ning Weng and Tilman Wolf U Massachusetts - Amherst Analysis of Traffic Traces for Stateful Applications Javier Verdu, Jorge Garcia, Mario Nemirovsky and Mateo Valero UPC, Tidal Networks 12:00-1:30 : Lunch 1:30-3:00 : Session 5, Hardware 2 A High-speed, Multi-threaded TCP Offload Engine for 10Gbps Ethernet Yatin Hoskote, Sriram Vangal, Vasantha Erraguntla and Nitin Borkar Intel A Hardware Platform for Network Intrusion Detection and Prevention Chris Clark, Wenke Lee, David Schimmel, Didier Contis, Mohamed Kone and Ashley Thomas Georgia Tech Packet Processing on a SIMD Stream Processor Jathin S. Rai, Yu-Kuen Lai, and Gregory T. Byrd NC State 3:00-3:30 : Break 3:30-5:00 : Session 6, Software A Programming Environment for Packet-processing Systems: Design Considerations Harrick Vin, Jayaram Mudigonda, Jamie Jason, Erik J. Johnson, Roy Ju, Aaron Kunze and Ruiqi Lian UT-Austin, Intel, Chinese Academy of Sciences RNOS: A Middleware Platform for Low Cost Packet Processing Devices Jonas Greutert and Lothar Thiele Netmodule, ETH Zurich On the Feasibility of Using Network Processors for DNA Queries Herbert Bos and Kaiming Huang Vrije U, U Leiden 5:00-5:15 : Short Break 5:15-6:30 : Industry Panel PROGRAM COMMITTEE Alan Berenbaum, Agere Brad Calder, UCSD Andrew Campbell, Columbia University Patrick Crowley, Washington University in St. Louis Jordi Domingo, UPC (Spain) Mark Franklin, Washington University in St. Louis Jorge Garcia, UPC (Spain) Haldun Hadimioglu, Polytechnic University Marco Heddes, Transwitch Corporation Manolis Katevenis, University of Crete (Greece) Bill Mangione-Smith, UCLA Kenneth Mackenzie, Reserviour Labs John Marshall, Cisco Daniel Mlynek, EPFL (Switzerland) Peter Z. Onufryk, IDT Lothar Thiele, ETH Zurich (Switzerland) Jon Turner, Washington University in St. Louis Mateo Valero, UPC (Spain) Tilman Wolf, University of Massachusetts ORGANIZERS Patrick Crowley, Washington University in St. Louis (pcrowley@cse.wustl.edu) Mark Franklin, Washington University in St. Louis (jbf@ccrc.wustl.edu) Haldun Hadimioglu, Polytechnic University (haldun@photon.poly.edu) Peter Z. Onufryk, IDT (peter.onufryk@idt.com) NP2 at HPCA 9 (2003) http://www.cs.washington.edu/NP2/ Selected papers from NP2 and additional industry contributions appear in Network Processor Design : Issues and Practices Volume II (Morgan Kaufmann Publishers, October 2003). NP1 at HPCA 8 (2002) http://www.cs.washington.edu/NP1/ Selected papers from NP1 and additional industry contributions appear in Network Processor Design : Issues and Practices Volume I (Morgan Kaufmann Publishers, September 2002). _____________________________________________________________________ To be removed from the npw-announce list, send mail to npw-announce-admin@cs.washington.edu (or reply to this message) with both "REMOVE" in the subject line and the email address to be removed in the message body.